The present technology relates to a comparator, a single slope type AD (analog-digital) converter, a solid-state imaging device typified by a CMOS (complementary metal-oxide semiconductor) image sensor, and a camera system.
There has been an increasing desire for the sophistication of signal processing and miniaturization of semiconductor devices having a structure in which a plurality of sensors are arranged in the form of an array, such as CMOS image sensors and the like.
In order to realize this, Japanese Patent Laid-Open No. 2011-159958, for example, proposes a method of integrating larger signal processing circuits with a chip size equal to that in the past by forming chips into a laminated structure.
Such a semiconductor device has a laminated structure of a chip including a sensor array for generating an analog signal (which chip will hereinafter be described as an analog chip) and a chip including a logic circuit for signal processing (which chip will hereinafter be described as a digital chip).
The miniaturization of the semiconductor device is achieved by vertically laminating these chips in a structure in which connection is established by TC(S)Vs (Through Contact (Silicon) VIAs) formed in the analog chip.
When the miniaturization is achieved by such a method, there is a problem of how to allocate circuit blocks relating to signal paths for passing data output from the sensor array to the upper and lower chips.
In a system as described above, the number of pieces of wiring for extracting signals from the sensor array is of the same order as the number of pixels in a vertical or horizontal direction in an image sensor, for example, and is thus a few thousand or more.
Therefore, when TCVs are inserted into these paths, the TCVs may inevitably need to be arranged densely. Hence, when the signal of a TCV adjacent to a certain TCV makes a transition with a large amplitude, the signal of the TCV of interest is subjected to interference, and an error occurs.
Measures against this interference have been made in the past by limiting signals transmitted via TCVs to signals quantized in a voltage direction (one or a plurality of binary signal lines are used).
Details of these measures will be described in the following.
The following description will first be made of measures in which transmission signals passing through TCVs are temporally discrete and quantized signals, that is, digital signals, and secondly be made of a case in which transmission signals passing through TCVs are temporally continuous but quantized signals.
Description will first be made of measures in which transmission signals passing through TCVs are temporally discrete and quantized signals, that is, digital signals.
FIG. 1 is a diagram showing a first example of configuration of a semiconductor device using a laminated chip in which transmission signals passing through TCVs are temporally discrete and quantized signals.
The semiconductor device 1 has a laminated structure of an analog chip 2 and a digital chip 3.
The semiconductor device 1 has a plurality of sensors 4 (−0, −1, . . . ) arranged in the form of an array on the analog chip 2 manufactured by using an analog process, the analog chip 2 being one of the chips of the laminated structure.
Sampling switches 6 (−0, −1, . . . ) for temporally discretizing signals are connected to the respective outputs of the sensors 4 via amplifiers 5 (−0, −1, . . . ).
In this case, when the signals output from the sensors 4 as sources have sufficiently high power, the outputs of the sensors may be directly connected to the sampling switches without the interposition of the amplifiers.
The signals temporally discretized by the sampling switches 6 are quantized in a voltage direction by using quantizers 7 (−0, −1, . . . ).
The quantizers 7 are formed by a plurality of comparators. Each of the comparators quantizes the signal by comparing a certain signal level with the level of the input signal.
In this case, the quantizers 7 may not complete the quantization at a time, but may be a circuit composed of a plurality of stages.
The signals digitized in such a process are transmitted to the digital chip 3 via TCVs 8 (−0, −1, . . . ), and processed by a digital signal processing circuit 9.
In this case, the signals passing through the TCVs 8 are binarized into a power supply level or a ground (GND) level, and cause no error unless the signals change by a magnitude of about half of a power supply voltage. In addition, even if a signal delay occurs due to the parasitic capacitance of the TCVs 8, no problem is presented when the signal delay is within a setup margin of the signal processing circuit 9.
Description will next be made of another example of configuration in which signals transmitted via TCVs are digital signals.
FIG. 2 is a diagram showing a second example of configuration of a semiconductor device using a laminated chip in which transmission signals passing through TCVs are temporally discrete and quantized signals.
In the semiconductor device 1A in this case, the output signals of sensors 4 are not directly discretized temporally by sampling switches 6, but are temporally discretized by SH (sample and hold) circuits 10 (−0, −1, . . . ) nearest to the sensors 4.
The sample and hold circuits 10 in a simplest form are realized by a switch and a capacitance only.
Description will next be made of a case where the example of configuration of FIG. 2 in which the signals transmitted via the TCVs are digital signals is applied to an image sensor.
FIG. 3 is a diagram showing a third example of configuration of a semiconductor device using a laminated chip in which transmission signals passing through TCVs are temporally discrete and quantized signals, and is a diagram showing an example in which the example of configuration of FIG. 2 is applied to a CMOS image sensor.
Incidentally, in FIG. 3, the same constituent parts as in FIG. 1 and FIG. 2 are identified by the same reference numerals in order to facilitate understanding.
A mainstream CMOS image sensor is of a column-parallel output type in which the CMOS image sensor has an FD amplifier in each pixel and one row in a pixel array is selected to read out the outputs of the row in a column direction simultaneously.
This is because it is difficult to obtain a sufficient driving capability with the FD amplifier disposed within the pixel and it is therefore necessary to lower a data rate, to which parallel processing is considered to be advantageous.
Such a CMOS image sensor 20 includes a pixel array section 21 as a sensor array and a row selecting circuit (V-scanner) 22 for driving the pixels.
The pixel array section 21 has pixel circuits 30 arranged in the form of a matrix with M rows and N columns.
The row selecting circuit 22 controls the operation of pixels arranged in an arbitrary row in the pixel array section 21. The row selecting circuit 22 controls the pixels through control lines LSEL, LRST, and LTRG.
FIG. 3 represents a case where a pixel circuit 30 is formed with four transistors as an example.
The pixel circuit 30 includes a photoelectric conversion element 31 formed by a photodiode (PD), for example (which photoelectric conversion element may hereinafter referred to simply as a PD). The pixel circuit 30 includes four transistors, that is, a transfer transistor 32, a reset transistor 33, an amplifying transistor 34, and a selecting transistor 35 as active elements for the one photoelectric conversion element 31.
In the CMOS image sensor 20, the functions of a sample and hold circuit in the block diagram of FIG. 2 are realized by a floating diffusion (capacitance) FD and the transfer transistor (transfer switch) 32 for the photoelectric conversion element (photodiode) 31 as a sensor.
Description will secondly be made of a case in which transmission signals passing through TCVs are temporally continuous but quantized signals.
FIG. 4 is a diagram showing a first example of configuration of a semiconductor device using a laminated chip in which transmission signals passing through TCVs are temporally continuous but quantized signals.
The semiconductor device 1C of FIG. 4 converts analog signals output from sensors 4 into signals on a time axis by comparing signals discretized by SH circuits 10 as in the semiconductor device 1A of FIG. 2 with a ramp wave generated by a ramp signal generator not shown in the figure in comparators 23 (−0, −1, . . . ).
The quantized sensor signals thus converted are transmitted to a digital chip 3C via TCVs 8, and the information on the time axis is quantized by counters (TDC) 24, whereby digital signals are obtained.
The above operation is shown by waveforms on the time axis as in FIG. 5.
A result of comparison between an analog signal and the ramp wave RAMP is output as a signal S23 from a comparator 23, thereby stopping the counting operation of a counter 24, and determining a signal. In this case, the start timing of the ramp wave RAMP and the start time of the counting operation of the counter 24 are synchronized with each other. Thus, this operation converts voltage information into temporal information.
When such a transmission method is used, the signals passing through the TCVs 8 are quantized into a power supply level/GND level as in the case where the signals transmitted via the TCVs are digital signals.
FIG. 6 is a diagram showing an example in which the configuration of FIG. 4 in the semiconductor device using the laminated chip is applied to a CMOS image sensor.
Incidentally, in FIG. 6, the same constituent parts as in FIG. 3 and FIG. 4 are identified by the same reference numerals in order to facilitate understanding.
As in the case of FIG. 4, analog signals output from pixels 30 are converted into signals on a time axis by comparing a ramp wave generated by a ramp signal generator 25 in comparators 23 (−0, −1, . . . ).
The quantized sensor signals thus converted are transmitted to a digital chip 3D via TCVs 8, the information on the time axis is quantized by counters (TDC) 24, and the resulting digital signals are retained by latches (memories) 26.
The digital signals retained by the latches 26 are horizontally transferred through a transfer line by a signal processing circuit 9.
Incidentally, a so-called single slope type AD converter (ADC) is formed by a comparator 23, a counter 24, and a latch 26 disposed in each column.
FIG. 7 is a diagram showing a configuration of an ordinary single slope type AD converter.
The single slope type AD converter 40 in FIG. 7 includes a comparator 41, a counter 42, and a ramp signal generator 43.
As described above, the single slope type AD converter 40 performs AD conversion by comparing a ramp wave (slope signal) from the ramp signal generator 43 such as a DAC or the like with an AD converter input signal IN in the comparator 41 and controlling the counter 42 in a subsequent stage.
There is a noise characteristic as an important performance index of the AD converter 40. The noise characteristic of the comparator 41 often governs the noise characteristic of the AD converter 40. Noise includes thermal noise, which is noise in a wide band, and flicker noise, RTS (Random-Telegraph-Signal) noise, and the like as low-frequency noise. These noises each degrade the noise characteristic.
A method of increasing transistor size and a method of inserting a mirror capacitance into the first-stage output of a comparator (see Japanese Patent Laid-Open No. 2010-93641) are generally known as methods for reducing these noises.